What generates VCD simulation files?

Value Change Dump (VCD) files are generated by standard digital logic simulators like Icarus Verilog, Verilator, ModelSim, and GHDL to record signal transitions during testbench runs.

Does this tool support multi-bit buses?

Yes. The viewer displays multi-bit buses (e.g. 8-bit counters or 32-bit data lines) with cross-hatched polygon transitions and hexadecimal values.

VCD Waveform Viewer & Digital Logic Simulator

Render Value Change Dump (.vcd) simulation waveforms directly in your browser. Inspect Verilog/VHDL logic clocks, digital buses, signal transitions, and cursor timing measurements offline.

Timescale 1 ns

Total Signals 0

Sim Duration 0 ns

Cursor Position 0 ns

LOGIC TIMING WAVEFORM DISPLAY Drag to pan • Click to place cursor

PASTE VCD FILE CONTENT

Frequently Asked Questions

How do I measure time between two clock edges?

Click anywhere on the waveform canvas to place the timing cursor. The cursor value displays in the top metrics bar in nanoseconds or picoseconds depending on the $timescale.

Is my simulation data private?

Yes. The entire VCD lexical parser and Canvas renderer run exclusively within your browser window with zero network activity.